sPyNNaker neural_modelling  7.4.2
delay_extension.h
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1 /*
2  * Copyright (c) 2017 The University of Manchester
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * https://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
21 
22 #ifndef __DELAY_EXTENSION_H__
23 #define __DELAY_EXTENSION_H__
24 
25 #include <common-typedefs.h>
26 
28 typedef enum region_identifiers {
30  SYSTEM = 0,
38 
42  uint32_t has_key;
43  uint32_t key;
44  uint32_t incoming_key;
45  uint32_t incoming_mask;
46  uint32_t n_atoms;
47  uint32_t n_delay_stages;
48  uint32_t n_delay_in_a_stage;
49  uint32_t clear_packets;
50  uint32_t n_colour_bits;
51 };
52 
57 #define pack_delay_index_stage(index, stage) \
58  ((index & 0xFF) | ((stage & 0xFF) << 8))
59 
63 #define unpack_delay_index(packed) (packed & 0xFF)
64 
68 #define unpack_delay_stage(packed) ((packed >> 8) & 0xFF)
69 
70 #endif // __DELAY_EXTENSION_H__
uint32_t clear_packets
Clear packets each timestep?
uint32_t incoming_key
Key to accept messages with.
region_identifiers
region identifiers
@ TDMA_REGION
tdma data
@ PROVENANCE_REGION
Provenance recording region.
@ SYSTEM
General simulation system control.
@ DELAY_PARAMS
Delay parameters (see delay_parameters)
uint32_t incoming_mask
Mask to filter delay_parameters::incoming_key.
uint32_t has_key
bool for if this vertex has a key.
uint32_t n_colour_bits
The number of bits used for colour.
uint32_t n_delay_in_a_stage
Number of delays in a given stage.
uint32_t key
Key to use for sending messages.
uint32_t n_atoms
Number of atoms.
uint32_t n_delay_stages
Number of delay stages.
Delay configuration, as read from SDRAM where it was placed by DSG or by on-chip generation.